Vertical heterojunction bipolar transistor

ABSTRACT

A heterojunction bipolar transistor ( 20, 60 ) is provided with a silicon (Si) base region ( 34, 74 ) that forms a semiconductor junction with a multilayer emitter ( 38 ) having a thin gallium arsenide (GaAs) emitter layer ( 36, 72 ) proximate the base region ( 34, 74 ) and a distal gallium phosphide (GaP) emitter layer ( 40, 66 ). The GaAs emitter layer ( 36, 72 ) is sufficiently thin, preferably less than 200 Å, so as to be coherently strained. In one embodiment, the GaP emitter layer includes a doped region ( 70 ) that serves as the emitter and an undoped region ( 68 ) on which the intrinsic portion of the transistor ( 60 ) is formed.

RELATED PATENTS

[0001] The present invention is a Continuation of: “VerticalHeterojunction Bipolar Transistor,” Ser. No. 09/441,576, issued on Jul.23, 2002 as U.S. Pat. No. 6,423,990, which is a Continuation-In-Part of:“Method Of Forming Heterojunction Bipolar Transistor Having WideBandgap, Low Interdiffusion Base-Emitter Junction,” Ser. No. 09,267,252,filed on Mar. 12, 1999 and issued on Jan. 9, 2001 as U.S. Pat. No.6,171,920, which is a Division of: “Heterojunction Bipolar TransistorHaving Wide Bandgap, Low Interdiffusion Base-Emitter Junction,” Ser. No.08/939,487, filed on Sep. 29, 1997, and issued on Jun. 15, 1999 as U.S.Pat. No. 5,912,481, all of which are incorporated herein by reference.

TECHNICAL FIELD OF THE INVENTION

[0002] The present invention relates generally to heterojunction bipolartransistors (HBTs).

BACKGROUND OF THE INVENTION

[0003] Heterojunction bipolar transistors (HBTs) theoretically provideadvantages over conventional homojunction bipolar transistors byproviding a heterojunction between a base and emitter of a transistor. Aheterojunction is formed between two dissimilar semiconductor materials.Silicon (Si) exhibits a bandgap of around 1.12 eV, but a Si homojunctionhas no bandgap discontinuity at the junction. A bandgap discontinuitycan occur at a junction by using dissimilar semiconductor materials onopposing sides of the junction. From the perspective of an NPNtransistor, discontinuity in the valence band restricts hole flow fromthe base to the emitter, thus improving emitter injection efficiency andcurrent gain. To the extent that injection efficiency and current gainimprovements can be achieved, base region resistivity may be lowered(which lowers the base resistance) and emitter region resistivity may beraised (which lowers base-emitter junction capacitance) to create fasttransistors without significantly compromising other device parameters.Such fast transistors would be useful for high-speed digital, microwave,and other integrated circuit and discrete transistor applications.

[0004] In practice, HBT performance often falls far short of thetheoretical expectations. One conventional Si-based HBT reduces thebandgap of the base region by creating a base material having a narrowerbandgap than Si. In particular, a small amount of germanium (Ge) ismixed with Si in the base (Si_(1−x)Ge_(x)), and the emitter is morepurely Si. Unfortunately, the amount of bandgap difference (ΔEg) for asmuch as 20% Ge content in the base is only about 0.15 eV. This small ΔEgachieves only a small portion of the performance benefits that HBTstheoretically promise.

[0005] Slight improvements in HBT performance have been achieved byusing materials other than Si for the emitter of an HBT. Three emittermaterials which have been investigated for use in HBT transistors aresilicon carbide (SiC), which has a bandgap of 2.93 eV, gallium arsenide(GaAs) which has a bandgap of 1.42 eV, and gallium phosphide (GaP),which has a bandgap of 2.24 eV. Unfortunately, such materials havelattice constants that differ from Si. For example, SiC has a 20%lattice mismatch, GaAs has a 4% lattice mismatch, and GaP has a 0.34%lattice mismatch. Likewise, such materials have thermal expansioncoefficients that differ from Si. SiC has a thermal expansioncoefficient of about 2.6×10⁻⁶(°C.)⁻¹, while GaAs has a thermal expansioncoefficient of around 6.7×10⁻⁶(°C.)⁻¹, and GaP has a thermal expansioncoefficient of around 5.91×10⁻⁶(°C.)⁻¹. Because of these differences,only thin layers of these materials have been successfully grown on Siwithout the formation of significant defects. The maximum thickness fora low defect layer of SiC grown on Si is only a few angstroms (Å), andfor GaAs grown on Si is less than 200 Å. At these thicknesses or less,strain, which is caused by lattice mismatch, is contained by latticestretching rather than crystal defects. Thinner, low-defect thicknessesof these materials do not possess a sufficient thickness to protect thebase-emitter junction from shorting due to diffusion of metal from theemitter contact region. Thicker, high-defect thicknesses of thesematerials exhibit degraded junction performance due to an excessivenumber of defects.

[0006] The most successful HBT improvements to date are believed to havebeen achieved by forming a GaP layer over Si at the base-emitterjunction. GaP is desirable because it has a relative large bandgap(i.e., about 2.24 eV) and little lattice mismatch with silicon (i.e.,about 0.34%). Nevertheless, such conventional HBTs that use a GaP layerover Si still achieve only a small portion of the performance benefitsthat HBTs theoretically promise. The reason for this poor performanceappears to be that a Si-GaP junction suffers from an unusually largeamount of interdiffusion, where the Ga and P readily diffuse into theSi, and vice-versa. The interdiffusion between Si and GaP results in apoor semiconductor junction, with the metallurgical junction beingdisplaced from the electrical junction. Accordingly, the performancegains that are suggested by the wide bandgap difference between a Sibase and a GaP emitter are not achieved in practice because theresulting diffuse junction negates those potential gains.

[0007] In the field of photoelectric semiconductors, it is desirable toform compound structures using a Si substrate and direct gapsemiconductor materials. A Si substrate is desirable for mechanicalstability and because a manufacturing infrastructure exists for reliablymass producing rugged Si wafers at relatively low cost. The Si substrateis typically an extrinsic part of the photoelectric semiconductor notused in forming intrinsic photoelectric semiconductor junctions.

[0008] Compound structures using a Si substrate and direct gapsemiconductor materials suffer from problems similar to those discussedabove for HBTs. Namely, lattice constant and thermal expansioncoefficients for direct gap semiconductors differ from Si. Consequently,in attempting to produce low-defect compound semiconductors havingdirect gap semiconductors and a Si substrate, conventional photoelectricsemiconductors often include very thick, highly doped buffer layersbetween the Si substrate and direct gap materials. Such buffer layersmay include indirect gap materials, such as GaP and others, but theseindirect gap materials are unsuitable for intrinsic photoelectricsemiconductors.

[0009] Such buffer layers tend to incrementally shift lattice constantsand thermal expansion coefficients so that the intrinsic direct gapphotoelectric semiconductor materials may then be grown with fewerdefects. Such applications often form relatively thick buffer layerswhich themselves may have numerous defects, at least closer to a Siinterface, that are of little consequence to the intrinsic photoelectricsemiconductor. Needless to say, such buffer layers are not used informing semiconductor junctions.

[0010] U.S. Pat. No. 5,912,481, which describes prior work of theinventors of the present invention, describes an HBT that goes a longway toward providing performance benefits that HBTs theoreticallypromise. However, further improvements in speed, radiation tolerancecharacteristics, and thermal dissipation would be desirable.

[0011] Speed and radiation tolerance characteristics can both beenhanced by using an improved substrate in which, or on which, anintrinsic transistor is formed. Conventional techniques apply a siliconon insulator (SOI) technology. Typically, an intrinsic transistor isformed over an SiO₂ layer rather than over a semiconductor, such as Si.When hit by radiation, the SiO₂ layer does not produce the electrondisturbances that are characteristic of a semiconductor, leading toradiation tolerance improvements. In addition, the insulative SiO₂ layerlowers capacitance, which leads to improvements in speed. However, SiO₂is not a particularly good thermal conductor. Consequently, less heat isconducted away from the intrinsic transistor, fewer transistors can beplaced near one another on an integrated circuit, and higher powerdevices are not practical.

[0012] Moreover, one conventional SOI technique forms a crystallinelayer (e.g., Si) used in the formation of intrinsic transistors over theSiO₂ layer. Since Sio₂ is a porous material, not a crystalline material,the overlying crystalline layer often exhibits defects that cannot becured by annealing. Accordingly, poor yields result. Anotherconventional SOI technique forms a single Si crystal, then implantsoxygen (O₂) under high energy deep into the Si crystal and anneals toform a deep SiO₂ layer. Unfortunately, getting complete and uniform SiO₂formation within an existing Si layer is extremely difficult.Consequently, this SOI technique is characterized by incompleteoxidation, which leads to a poor quality SiO₂ layer and only marginalspeed and radiation tolerance improvements.

SUMMARY OF THE INVENTION

[0013] Accordingly, it is an advantage of the present invention that animproved heterojunction bipolar transistor (HBT) having a wide bandgapwith low interdiffusion base-emitter junction and method therefor areprovided.

[0014] Another advantage is that an HBT having a multilayer emitter isprovided.

[0015] Another advantage is that an HBT is provided which has a widebandgap emitter along with a base-emitter junction that is substantiallyfree of interdiffusion.

[0016] Another advantage is that an HBT is provided with a Si baseregion that forms a junction with a multilayer emitter having a thinGaAs layer proximate the base region and a distal GaP layer.

[0017] Another advantage is that an HBT is provided that exhibitsperformance that more closely meets theoretical expectations thanconventional HBTs.

[0018] Another advantage is that an HBT is provided which uses a Sisubstrate and a substantially insulative crystalline layer grownthereon.

[0019] Another advantage is that an intrinsic HBT is formed in and on asubstantially insulative layer that is also a good thermal conductor.

[0020] The above and other advantages of the present invention arecarried out in one form by a vertical heterojunction bipolar transistorwhich includes a gallium phosphide layer (GaP) configured to exhibit afirst conductivity type. The GaP layer forms a first portion of amultilayer emitter. A gallium arsenide (GaAs) layer is formed in contactwith the GaP layer. The GaAs layer forms a second portion of themultilayer emitter. A silicon (Si) base region of a second conductivitytype is formed in contact with the GaAs layer. In addition, a Sicollector region of the first conductivity type is formed adjacent tothe Si base region.

BRIEF DESCRIPTION OF THE DRAWINGS

[0021] A more complete understanding of the present invention may bederived by referring to the detailed description and claims whenconsidered in connection with the Figures, wherein like referencenumbers refer to similar items throughout the Figures, and:

[0022] FIGS. 1-10 show sectional views of a first embodiment of an HBTat first through tenth processing stages, respectively;

[0023]FIG. 11 shows a schematic, zero biased, band diagram of acomposite emitter HBT according to a preferred embodiment of the presentinvention; and

[0024] FIGS. 12-18 show sectional views of a second embodiment of an HBTat first through seventh processing stages, respectively.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] FIGS. 1-10 show sectional views of a heterojunction bipolartransistor (HBT) 20 configured in accordance with the present inventionat first through tenth processing stages, respectively. The Figuresillustrate an NPN implementation of the present invention, but thoseskilled in the art will realize that an equivalent PNP implementation iseasily achieved by making routine substitutions well known to thoseskilled in the art.

[0026]FIG. 1 illustrates a first processing stage in which a buriedregion 22 is formed in a silicon (Si) substrate 24. Preferably,substrate 24 is lightly doped P-type conductivity, and buried region 22is heavily doped through a standard ion implantation process to exhibitN-type conductivity for this NPN implementation.

[0027]FIG. 2 illustrates a second processing stage that follows thefirst processing stage depicted in FIG. 1. As illustrated in FIG. 2, acollector layer 26 is epitaxially grown on substrate 24. Buried region22 is now diffused into both collector layer 26 and substrate 24.Collector layer 26 is a lightly doped N-type conductivity. Phosphorous,antimony, or arsenic N-type dopants are used through conventionaltechniques, such as ion implantation or diffusion, to achieve thedesired conductivity type. Buried region 22 allows collector layer 26 toexhibit a low resistance while controlling the breakdown voltage of HBT20. As understood by those skilled in the art, the thickness ofcollector layer 26 is selected to achieve application-specific goals.For example, collector layer 26 is desirably thinner to increase thespeed of HBT 20 and thicker to increase the breakdown voltage of HBT 20.

[0028]FIG. 3 illustrates a third processing stage that follows thesecond processing stage depicted in FIG. 2. FIG. 3 shows severalindependent diffusion areas formed in collector layer 26. A highly dopedP-type conductivity isolation diffusion area 28 is made to surround acollector region 30, which provides proper isolation for the final HBT20. Collector region 30 will eventually serve as the collector of HBT20. Diffusion area 28 desirably refrains from overlying any portion ofburied region 22.

[0029] A highly doped N-type conductivity contact-enabling diffusionarea 32 is made at a location within collector region 30 where ametallization layer will eventually make an electrical collectorcontact. This location desirably overlies a portion of buried layer 22.

[0030] A base region 34 is another diffusion area that is also formedwithin collector region 30. Base region 34 will eventually serve as thebase of HBT 20. Base region 34 is doped to exhibit P-type conductivityfor this NPN implementation. Desirably, base region 34 is heavily dopedso that the base of HBT 20 will exhibit an unusually low resistance.Diffusion areas 28, 32, and 34 are formed using conventional ionimplantation or other techniques. Isolation and contact-enablingdiffusion areas 28 and 32 are desirably formed using a much higheracceleration voltage than base region 34 to drive diffusion areas 28 and32 deeper into collector layer 26 than base region 34.

[0031] In an alternative embodiment, a small amount of germanium (Ge) ismixed with the Si of base region 34 to lower the bandgap of the base ofHBT 20 when compared to the bandgap of a base formed using more pure Si.This mixing is desirably performed during the second stage depicted inFIG. 2. Small amounts of Ge (e.g., around 10%) with a P+ type doping canbe mixed with the Si during only the later portion of epitaxial growthfor collector layer 26 to form the base.

[0032]FIG. 4 illustrates a fourth processing stage that follows thethird processing stage depicted in FIG. 3. FIG. 4 illustrates heat beingapplied to further drive diffusion areas 28, 32, and 34 deeper intocollector layer 26. Isolation diffusion area 28 is desirably driventhrough collector layer 26 to substrate 24. Contact-enabling diffusionarea 32 is desirably driven through collector region 30 to buried region22. However, base region 34 is desirably driven only a shallow depthinto collector layer 26. Desirably, base region 34 is around 1000 Ådeep. However, the resulting base of HBT 20 will be shallower than thisdepth due to subsequent etching steps. This shallow depth of base region34 leads to a low transit time, which increases the high current gaincut-off frequency (Ft) and high power gain cut-off frequency (Fmax)parameters for HBT 20.

[0033] During this fourth stage of processing, heat in excess of 800° C.may be applied to HBT 20 for extended periods of time. However, afterthis stage the temperature of HBT 20 is desirably maintained below 800°C. to prevent diffusion of non-silicon layers that will be grown overcollector layer 26.

[0034]FIG. 5 illustrates a fifth processing stage that follows thefourth processing stage depicted in FIG. 4. FIG. 5 actually illustratestwo epitaxial growth processes. The first epitaxial growth process growsa wide bandgap, non-silicon semiconductor, preferably gallium arsenide(GaAs), over and in contact with collector layer 26 to form a firstemitter layer 36 of a multilayer emitter 38 (see FIG. 6). First emitterlayer 36 may be of N-type conductivity for this NPN implementation ormay not be intentionally doped, but is desirably configured so as not toexhibit P-type conductivity. A function of first emitter layer 36 is adiffusion barrier to provide a stable interface with the Si of baseregion 34.

[0035] The second epitaxial growth process grows a second non-silicon,wide bandgap semiconductor, preferably gallium phosphide (GaP), over andin contact with first emitter layer 36 to form a second emitter layer 40of multilayer emitter 38. Desirably, second emitter layer 40 isdegeneratively doped with a suitable N-type conductivity material forthis NPN implementation, such as Si, to values in excess of 10×1020/cm³to provide a very low emitter contact resistance where a metallizationlayer will eventually make an electrical emitter contact. Desirably,doping gradually increases as second emitter layer 40 builds away fromfirst emitter layer 36 to reach the maximum value at the distal surfacefrom first emitter layer 36. The function of second emitter layer 40 isto provide maximum valence band discontinuity with minimum latticemismatch and minimal thermal expansion mismatch with respect to Si.

[0036] GaAs is a desirable material for use as an interface with Sibecause it can form an interface substantially free from interdiffusion,particularly when compared to the interdiffusion that results fromforming a GaP layer on Si. In other words, an atomically abruptinterface forms between GaAs first emitter layer 36 and base region 34.Desirably, first emitter layer 36 is epitaxially grown usingconventional techniques but at a relatively low temperature (e.g.,400-600° C.) to keep the Si—GaAs junction as free from interdiffusion aspossible. Alternative cycles of even lower temperatures (e.g., 150-250°C.) may be applied during the growth process. This results in asubstantially pure crystalline structure suitable for intrinsicsemiconductor activity.

[0037] Moreover, first emitter layer 36 is limited in thickness so thatfirst emitter layer 36 will be coherently strained between the Si ofbase region 34 and second emitter layer 40. Thickness is limited in amanner understood to those skilled in the art by controlling the timeover which first emitter layer 36 is grown. A coherently strained layeris a layer so thin that lattice constant mismatches do not result inlattice mismatch crystal defects but are contained by latticestretching. With first emitter layer 36 made from GaAs and secondemitter layer 40 made from GaP, a thickness for first emitter layer 36of less than 200 Å is preferred, with a thickness of less than 50 Åbeing particularly desirable.

[0038] The thickness of second emitter layer 40 is desirably muchgreater than the thickness of first emitter layer 36. Second emitterlayer 40 is desirably at least 500 Å thick, and preferably around2000-3000 Å thick. Less overall thickness is desired for multilayeremitter 38. Less thickness leads to a smaller emitter resistance and afaster HBT 20. However, the thickness of multilayer emitter 38, andprimarily second emitter layer 40, is balanced with a need to preventthe emitter and base of HBT 20 from shorting. Shorting can occur whenmetallization, discussed below, diffuses through multilayer emitter 38to reach base region 34. A sufficient thickness for second emitter layer40 prevents metallization from diffusing therethrough.

[0039] Second emitter layer 40 is desirably grown epitaxially usingstandard techniques at temperatures that generally remain in the400-600° C. range to preserve the substantially interdiffusion-freeinterface between first emitter layer 36 and base region 34. Althoughnot shown, toward the upper regions of second emitter layer 40, distallyremoved from first emitter layer 36, temperature may be lowered so thatthis portion of second emitter layer 40 becomes polycrystalline. Amongother benefits, this lessens the time HBT 20 spends at elevatedtemperatures to further lessen risks of interdiffusion at thebase-emitter junction.

[0040] While first emitter layer 36 provides an abrupt interface with Sibase region 34, second emitter layer 40 provides as great of a bandgapdiscontinuity as is practical. Thus, the bandgap characteristics of HBT20 in the vicinity of the base-emitter junction are determined primarilyby the bandgap differences between materials used for base region 34 andsecond emitter layer 40. However, the abruptness of the base-emitterjunction (i.e., the congruence of the metallurgical and electricaljunctions) is determined primarily by materials used for base region 34and first emitter layer 36.

[0041] Due to the thin, coherently strained nature of first emitterlayer 36, base region 34 exhibits few defects. Likewise, second emitterlayer 40, although relatively thick, exhibits few defects in partbecause first emitter layer 36 is sufficiently thin to be coherentlystrained. Accordingly, not only does first emitter layer 36 provide aclean, abrupt semiconductor junction at base region 34, but firstemitter layer 36 allows second emitter layer 40 to be epitaxially grownto a relatively thick width with few defects.

[0042]FIG. 6 illustrates a sixth processing stage that follows the fifthprocessing stage depicted in FIG. 5. FIG. 6 shows a patterning andetching process. Conventional photolithographic techniques can be usedto pattern HBT 20, then etching is performed to remove portions of firstand second emitter layers 36 and 40 that will not be used for multilayeremitter 38.

[0043]FIG. 7 illustrates a seventh processing stage that follows thesixth processing stage depicted in FIG. 6. FIG. 7 shows a passivationprocess. Conventional techniques are used to apply a passivation layer42 over the entire surface of HBT 20 at this point. Silicon nitride,silicon dioxide, or other conventional passivation materials may beapplied in a conventional manner, so long as temperatures generallyremain below about 800° C.

[0044]FIG. 8 illustrates an eighth processing stage that follows theseventh processing stage depicted in FIG. 7. FIG. 8 shows anotherpatterning and etching process. Conventional photolithographictechniques can be used to pattern HBT 20, then etching is performed toremove passivation layer 42 to form vias 44 in locations where ametallization layer will eventually make electrical contacts.

[0045]FIG. 9 illustrates a ninth processing stage that follows theeighth processing stage depicted in FIG. 8. FIG. 9 shows a metallizationprocess that uses conventional techniques to deposit a metallizationlayer 46 over the entire surface of HBT 20.

[0046]FIG. 10 illustrates a tenth processing stage that follows theninth processing stage depicted in FIG. 9. FIG. 10 shows yet anotherpatterning and etching process. Conventional photolithographictechniques can be used to pattern HBT 20, and then etching is performedto remove metallization layer 46 where not wanted over the surface ofHBT 20. However, metallization layer 46 remains within and over vias 44to form electrical contacts with the base, collector, and emitterregions of HBT 20.

[0047]FIG. 11 shows a schematic, zero biased, band diagram for HBT 20.FIG. 11 depicts a conduction band (E_(c)) trace 48 and a valence bandtrace (E_(v)) 50 on vertically opposing sides of a Fermi level (E_(f))52. The band diagram of FIG. 11 is horizontally partitioned into foursections 30′, 34′, 36′, and 40′ corresponding to collector region 30,base region 34, first emitter layer 36, and second emitter layer 40(FIG. 10), respectively.

[0048] Referring to FIGS. 10-11, in collector region 30 the bandgapenergy equals E_(c)−E_(v), or approximately 1.12 eV. In base region 34the bandgap energy still equals approximately 1.12 eV. In other words,base region 34 has roughly the same bandgap as collector region 30.

[0049] In first emitter layer 36, the bandgap energy equalsapproximately 1.42 eV. This increase of roughly 0.3 eV from the bandgapof base region 34 and collector region 30 is due to the higher bandgapof GaAs compared to the bandgap of Si. Moreover, substantially all ofthis 0.3 eV appears as a discontinuity 54 in the valence band E_(v).Very little of the increase in bandgap achieved by transitioning from Sito GaAs in first emitter layer 36 appears in conduction band E_(c).

[0050] In second emitter layer 40, the bandgap equals approximately 2.24eV. This represents an increase of roughly 0.8 eV from the bandgap infirst emitter layer 36. Accordingly, another discontinuity in thebandgap energy results. This discontinuity is divided between a valenceband discontinuity 56 of approximately 0.5 eV and a conduction banddiscontinuity 58 of approximately 0.3 eV. The total bandgapdiscontinuity between second emitter layer 40 and base region 36 isapproximately 1.1 eV, with the majority of the discontinuity appearingin the valence band E_(v). The majority of the discontinuity appearingin the valence band E_(v) is desirable for NPN transistors because it isthe parameter that characterizes the suppression of hole injection.

[0051] Not only does first emitter layer 36 provide a stable, abruptsemiconductor junction at base region 34 and simultaneously allow secondemitter layer 40 to be epitaxially grown with few defects, but firstemitter layer 36 also causes a larger portion of the total bandgapdiscontinuity between multilayer emitter 38 and base region 34 to appearas a valence band discontinuity, which is particularly useful insuppressing hole injection. This relatively large valence banddiscontinuity significantly suppresses hole injection from base region34 to multilayer emitter 38, creating an HBT with greatly improvedemitter injection efficiency compared to prior art HBTs.

[0052] FIGS. 12-21 show sectional views of an HBT 60 at first throughtenth processing stages, respectively. HBT 60 is an alternativeembodiment to HBT 20, discussed above. In general, HBT 60 is an upsidedown implementation of HBT 20, with an emitter region of the GaP layerbeing the bottom-most portion of the intrinsic transistor and beingsurrounded by a GaP region that is configured to be substantiallyinsulative. HBT 60 operates substantially in accordance with the banddiagram illustrated in FIG. 11.

[0053]FIG. 12 illustrates a first processing stage in which anon-silicon semiconductor layer 62, preferably gallium arsenide (GaAs)is epitaxially grown over and in contact with a silicon (Si) substrate64, and another non-silicon semiconductor layer 66, preferably galliumphosphide (GaP) is then epitaxially grown over and in contact with layer62. Preferably, substrate 64 is undoped and left to exhibit itsintrinsic doping so that it will exhibit low conductivity for improvedradiation tolerance and reduced capacitance with the intrinsictransistor, discussed below.

[0054] As with first emitter layer 36, discussed above in connectionwith the first embodiment, layer 62 is limited in thickness so that itwill be coherently strained between Si substrate 64 and layer 66. Withlayer 62 made from GaAs, a thickness of less than 200 Å is preferred,with a thickness of less than 50 Å being particularly desirable. Layer62 is extrinsic to HBT 60 and serves primarily as a buffer between Sisubstrate 64 and the above-layer. However, layer 62 also substantiallyprevents interdiffusion at the boundary between substrate 64 and layer62, and the formation of a conductive region due to any interdiffusion.

[0055] In an alternative embodiment (not shown), layer 62 may beomitted, and layer 66 grown to a greater thickness than would be neededwhen layer 62 is included. In this embodiment, defects are likely toform in layer 66 near substrate 64, but such defects are minimized aslayer 66 becomes thicker.

[0056] Layer 66 is preferably a wide bandgap semiconductor that exhibitsor can be selectively made to exhibit good insulative qualities andexhibits good or can be made to exhibit good thermal conductivityqualities. Preferably, GaP is used for layer 66. Desirably, layer 66 isgrown to a large thickness, preferably greater than 5000 Å when layer 62is present, but this is not a requirement of the present invention.Standard techniques, as discussed above in connection with the firstembodiment, may be used to grow layer 66.

[0057] As indicated by a dotted line in FIG. 12, layer 66 is dividedinto an undoped region 68 and a doped region 70. In undoped region 68,layer 66 is desirably formed to exhibit insulative properties, such asthe insulative properties demonstrated by GaP that exhibits only itsintrinsic doping [GaP(i)]. In doped region 70, layer 66 is desirablydoped to exhibit “N” type doping [GaP(n)] in this NPN example. Dopingmay be accomplished by adding a suitable dopant while growing dopedregion 70 of layer 66. Layer 66 exhibits increased conductivity in dopedregion 70 due to the doping.

[0058] In this embodiment, doped region 70 will provide an outsidelayer, which also serves as a penultimate inside layer, of a multilayeremitter 72 for HBT 60. Accordingly, doped region 70 is intrinsic to HBT60, but undoped region 68 is extrinsic to HBT 60 because it does nottake a substantial part in the electrical activity of HBT 60. Thefunction of doped region 70 is similar to that of second emitter layer40, discussed above in connection with the first embodiment.

[0059] The depth of doped region 70 in layer 66 desirably varies toachieve application goals. Generally, a high-speed transistor willbenefit from doped region 70 being relatively shallow so that emitterresistivity is raised and base-emitter junction capacitance is lowered.Moreover, a greater thickness for insulative, undoped region 68 isdesirable because it decreases capacitance with layers underlying theintrinsic transistor and improves radiation tolerance.

[0060]FIG. 13 illustrates a second processing stage that follows thefirst processing stage depicted in FIG. 12. In this second stage, athird non-silicon, semiconductor layer 74 is grown over and in contactwith layer 66. Layer 74 has a function similar to that of layer 36,discussed above. In particular, layer 74 provides an interdiffusionbarrier between layer 66 and subsequent Si layers, discussed below, andlayer 74 buffers between the different materials used for layer 66 inthe subsequent Si layers. Layer 74 is desirably formed substantially ofGaAs.

[0061] Layer 74 is limited in thickness so that layer 74 will becoherently strained between layer 66 and subsequent Si layers. Withlayer 74 made from GaAs and layer 66 made from GaP, a thickness forlayer 74 of less than 200 Å is preferred, with a thickness of less than50 Å being more desirable. Layer 74 may be lightly N-type doped for thisNPN implementation or may exhibit its intrinsic doping, but ispreferably configured not to intentionally exhibit P-type conductivity.Layer 74 provides an inside layer, which also serves as a penultimateoutside layer, of multilayer emitter 72 for HBT 60, and is therefore anintrinsic part of HBT 60.

[0062]FIG. 14 illustrates a third processing stage that follows thesecond processing stage depicted in FIG. 13. In this third stage, a Silayer 76 is epitaxially grown over and in contact with layer 74. Inaccordance with conventional processing techniques, layer 76 may begrown in a chamber separate from the chamber used to grow layers 62, 66,and 74 to minimize the risk of chamber contamination. In order to movethe wafer to a new chamber, a thin (e.g., 50 Å) Si layer (not shown) maybe temporarily grown on layer 74 to protect the exposed surface of layer74, then this temporary layer removed through etching when the wafer hasbeen moved into the new chamber.

[0063] Layer 76 is preferably grown to exhibit three regions ofdiffering conductivity type. A region 78, which will serve as the baseof HBT 60, is grown over and in contact with layer 74. The boundarybetween layer 74 and base region 78 will serve as the base-emitterjunction for HBT 60. Since layers 66 and 74 are non-silicon layers andbase 78 is a silicon layer, a heterojunction results.

[0064] Si layer 76 and subsequent processing stages are desirably grownwhile keeping temperatures below 800° C. to preserve an abruptbase-emitter junction. Base 78 is heavily doped to exhibit P-typeconductivity [Si(p+)] for this NPN implementation by adding a suitabledopant while growing base 78 of layer 66. Desirably, base 78 is heavilydoped so that the base of HBT 60 will exhibit an unusually lowresistance. A small amount of Ge may be mixed with the Si of base 78 tolower the bandgap of the base of HBT 60 when compared to the bandgap ofa base formed using more pure Si. Desirably, base 78 is grown to athickness greater than 1000 Å, with a thinner base 78 being moredesirable for higher speed characteristics.

[0065] Si layer 76 is grown to include a collector region 80 over and incontact with base 78. Collector 80 may be grown to a thickness ofgreater than 2000 Å, with less thickness being more desirable in lowervoltage applications. As a minimum, layer 76 needs to be sufficientlythick so that subsequent metallization does not diffuse throughcollector 80 to short with base 78. Collector 80 is lightly doped toexhibit N-type conductivity [Si(n−)] for this NPN implementation byadding a suitable dopant while growing collector 80.

[0066] Si layer 76 is also grown to include a collector-contact-enablingregion 82 over and in contact with collector region 80. Region 82 mayhave a thickness in the range of 1000-4000 Å. Region 82 differs fromregion 80 in that region 82 is highly doped [Si(n+)] to enable aninterface with a metal contact, to be applied later. Regions 80 and 82will be collectively referred to below simply as collector 80.

[0067]FIG. 15 illustrates a fourth processing stage that follows thethird processing stage depicted in FIG. 14. FIG. 15 shows a patterningand etching process. Conventional photolithographic techniques can beused to pattern HBT 60, then etching is performed to remove a portion ofregions 82 and 80 from Si layer 76 so that only the feature that will beused as collector 80 for HBT 60 remains. Desirably, etching is stoppedbelow heavily doped contact-enabling region 82 and somewhere in themiddle of the lightly doped region 80. The precise location for stoppingthe etching process is not a critical parameter. FIG. 15 illustrates HBT60 following the removal of a mask used in this etching process.Collector 80 will be centrally located in HBT 60.

[0068]FIG. 16 illustrates a fifth processing stage that follows thefourth processing stage depicted in FIG. 15. FIG. 16 shows a masking andion implantation process. Conventional photolithographic and etchingtechniques can be used to pattern and etch HBT 60 to form a suitablemask 84 (e.g., Si₃N₄), then ion implantation is performed inbase-contact-enabling areas 86. Implantation energies are adjusted tothat a highly conductive P-type dopant (p+) for this NPN example isdriven through the remaining portion of lightly doped Si(n−) region 80into, but not through, base 78 at base-contact-enabling areas 86. Thehighly conductive p+ dopant overwhelms the lightly conductive n− dopantto result in areas 86 being Si(p+). Implantation may occur in two steps,with a higher energy implantation step followed by a lower energyimplantation step. The higher energy step causes the dopant to be drivento a large depth and the lower energy step causes the dopant to bedriven only to a small depth so that base-contact-enabling areas 86 arecontinuous Si(p+) regions from the exposed surface down into base 78.

[0069]FIG. 17 illustrates a sixth processing stage that follows thefifth processing stage depicted in FIG. 16. Compared to the fifthprocessing stage of FIG. 16, mask 84 is removed, and conventionalphotolithographic and etching techniques have been performed to removeremaining portions of Si layers 78 and 80 not needed for base 78 orcollector 80. The removed portions are outside of base-contact-enablingareas 86. The remaining portion of layer 76 forms base 78 and collector80. After this patterning and etching step, a masking and ionimplantation process is performed to apply a suitable mask 88 (e.g.,Si₃N₄) which has openings in emitter-contact-enabling areas 90. Whenmask 88 has been applied, ion implantation is performed inemitter-contact-enabling areas 90 by driving a suitable highlyconductive n+ dopant for this NPN example through GaAs layer 74 intodoped region 70 of GaP layer 66.

[0070]FIG. 18 illustrates a seventh processing stage that follows thesixth processing stage depicted in FIG. 17. FIG. 18 shows isolation,passivation and metallization processes. In particular, FIG. 18 depictsetching of an isolation well 92, the application of a passivation layer94, and then the application of a metallization layer 96.

[0071] First, a suitable mask is applied (not shown) and well 92 etchedaround the perimeter of HBT 60 to isolate HBT 60 from other transistorsand devices (not shown) formed over substrate 64. Well 92 is etched intoinsulative (undoped) region 68 in layer 66, or deeper, for effectiveisolation. While the area surrounded by well 92 is not a criticalparameter of the present invention, a smaller area is desirable forhigher transistor density and faster performance.

[0072] Next, conventional techniques are used to apply passivation layer94 over the entire surface of HBT 60 at this point. Silicon nitride,silicon dioxide, or other conventional passivation materials may beapplied in a conventional manner, so long as temperatures generallyremain below about 800° C. Then, a patterning and etching process isperformed in which conventional techniques may be used to pattern HBT 60and remove selected portions of passivation layer 94 to form vias inlocations where metallization layer 96 will eventually make electricalcontacts with the emitter, base, and collector of HBT 60.

[0073] Finally, conventional techniques may be used to depositmetallization layer 96 over the entire surface of HBT 60. Afterdeposition of metallization layer 96, another patterning and etchingprocess removes metallization layer 96 where not wanted over the surfaceof HBT 60. However, metallization layer 96 remains within and over theabove-discussed vias to form an emitter contact 98 atemitter-contact-enabling areas 90, a base contact 100 atbase-contact-enabling areas 86, and a collector contact 102 at collector80. Collector contact 102 is centrally located (i.e., innermost) withinHBT 60. Base contact 100 is intermediately located within HBT 60 and maysubstantially surround collector contact 102. Emitter contact 98 isperipherally located (i.e., outermost) within HBT 60 and maysubstantially surround base contact 100 and collector contact 102. Inaddition, the pattern of metallization is configured so thatmetallization layer 96 is routed to other circuits and/or pads to makeHBT 60 usable in an electrical circuit.

[0074] Due to the thin, coherently strained nature of emitter layer 74,multilayer emitter 72 and base 78 exhibit few defects. Moreover,multilayer emitter 72 provides a clean, abrupt semiconductor junction atbase layer 78, and allows base 78 and collector 80 to be epitaxiallygrown to a relatively thick width with few defects. The band diagramdepicted in FIG. 11 applies for HBT 60 as discussed above for HBT 20.

[0075] Referring to FIGS. 10 and 18, HBT 60 (FIG. 18) is upside downrelative to HBT 20 (FIG. 10). In both HBT 20 and HBT 60 a multilayer,non-silicon emitter forms a base-emitter junction with a Si base, andthe collector, base, and emitter are arranged vertically. The emitter ison the top in HBT 20 (i.e., distally located relative to substrate 24),but on the bottom in HBT 60 (i.e., proximally located relative tosubstrate 64). In the preferred embodiments, GaP is used for theoutermost emitter layer that is intrinsic to HBTs 20 and 60.

[0076] In HBT 60 (FIG. 18), the intrinsic portion of GaP layer 66 isconfined to doped region 70. However, doped region 70, and the otherfeatures that are intrinsic to HBT 60, are spaced apart from substrate64 and from other HBTs 60 (not shown) which may be formed over the samesubstrate 64 by undoped region 68 of GaP layer 66. In the preferredembodiments, undoped region 68 exhibits the good insulative propertiesand good thermal conductivity properties characteristic of undoped GaP.Accordingly, the insulative properties promote lower parasiticcapacitance and improved speed along with less electron disturbance inthe presence of radiation and improved radiation tolerance. The goodthermal conductivity properties allow heat generated by the intrinsicportions of HBT 60 to be readily conducted to Si substrate 64, which isalso a good thermal conductor. Accordingly, a greater number of HBTs 60may be formed on substrate 64 or higher power HBTs 60 may be formed.

[0077] In summary, an improved HBT having a wide bandgap with a lowinterdiffusion base-emitter junction is provided along with methods forforming the HBT. The HBT uses a Si substrate, which is desirable becausethe use of a Si substrate takes advantage of the existing manufacturinginfrastructure that reliably produces relatively rugged Si wafers at lowcost.

[0078] A multilayer emitter is provided in the HBT. This emitterexhibits a wide bandgap, and the resulting base-emiter junction issubstantially free of interdiffusion. In a preferred embodiment, the HBTis provided with a Si base that forms a heterojunction with a multilayeremitter having a thin GaAs layer proximate the base and a distal GaPlayer. The base-emitter junction and the wide bandgap multilayer emittertogether allow an HBT configured in accordance with the presentinvention to exhibit performance more closely meeting theoreticalexpectations than does the performance of conventional HBTs. In oneembodiment, the HBT uses a Si substrate and a substantially insulativecrystalline layer grown thereon, with the features intrinsic to the HBTformed in and above this insulative crystalline layer.

[0079] The present invention has been described above with reference topreferred embodiments. However, those skilled in the art will recognizethat changes and modifications may be made in these preferredembodiments without departing from the scope of the present invention.For example, while the above-presented description discusses theformation of a single HBT, those skilled in the art will readilyrecognize that a multiplicity of HBTs may be simultaneously formed asdescribed above, or in an equivalent manner, for integrated circuit ordiscrete transistor applications. These and other changes andmodifications that are obvious to those skilled in the art are intendedto be included within the scope of the present invention.

What is claimed is:
 1. A vertical heterojunction bipolar transistorcomprising: a gallium phosphide layer (GaP) configured to exhibit afirst conductivity type, said GaP layer forming a first portion of amultilayer emitter; a gallium arsenide (GaAs) layer formed in contactwith said GaP layer, said GaAs layer forming a second portion of saidmultilayer emitter; a silicon (Si) base region of a second conductivitytype formed in contact with said GaAs layer; and a Si collector regionof said first conductivity type formed adjacent to said Si base region.2. A vertical heterojunction bipolar transistor as claimed in claim 1wherein said GaAs layer is less than 200 Å thick.
 3. A verticalheterojunction bipolar transistor as claimed in claim 1 wherein saidGaAs layer is sufficiently thin so as to be coherently strained.
 4. Avertical heterojunction bipolar transistor as claimed in claim 1 whereinsaid GaAs layer is configured so as not to exhibit said secondconductivity type.
 5. A vertical heterojunction bipolar transistor asclaimed in claim 1 wherein a base-emitter transistor junction located atan interface between said Si base region and said GaAs layer issubstantially free of interdiffusion.
 6. A vertical heterojunctionbipolar transistor as claimed in claim 1 wherein said GaAs layer andsaid GaP layer are epitaxially grown.
 7. A vertical heterojunctionbipolar transistor as claimed in claim 1 wherein said transistoradditionally comprises a Si substrate positioned underneath said GaPlayer.
 8. A vertical heterojunction bipolar transistor as claimed inclaim 7 wherein said GaAs layer is a first GaAs layer and saidtransistor additionally comprises a second GaAs layer between said Sisubstrate and said GaP layer.
 9. A vertical heterojunction bipolartransistor as claimed in claim 1 wherein: said GaP layer is configuredto have a first region doped to exhibit said first conductivity type,said first region of said GaP layer being in contact with said GaAslayer and forming said first portion of said multilayer emitter; andsaid GaP layer is configured to have a second region in contact withsaid second GaAs layer, said second region being substantially undoped.10. A vertical heterojunction bipolar transistor as claimed in claim 9wherein said first GaP region is intrinsic to said heterojunctionbipolar transistor and said second GaP layer is extrinsic to saidheterojunction bipolar transistor.
 11. A vertical heterojunction bipolartransistor as claimed in claim 1 wherein: said GaP layer is configuredto have a first region doped to exhibit said first conductivity type,said first region of said GaP layer being in contact with said GaAslayer and forming said first portion of said multilayer emitter; andsaid GaP layer is configured to have a second region in contact withsaid second GaAs layer, said second region being substantiallyinsulative.
 12. A vertical heterojunction bipolar transistor as claimedin claim 1 wherein: said GaAs layer is formed over said GaP layer; saidSi base region is formed over said GaAs layer; and said Si collectorregion is formed over said Si base region.
 13. A vertical heterojunctionbipolar transistor as claimed in claim 1 additionally comprising anemitter contact coupled to one of said GaAs layer and said GaP layer, abase contact coupled to said Si base region, and a collector contactcoupled to said Si collector region, wherein said emitter contact is anoutermost one of said emitter, base, and collector contacts, and saidcollector contact in an innermost one of said emitter, base, andcollector contacts.
 14. A vertical heterojunction bipolar transistorcomprising: a first non-silicon layer exhibiting a first conductivitytype and a bandgap wider than silicon, said first non-silicon layerforming a first layer of a multilayer emitter; a second non-siliconlayer in contact with said first non-silicon layer, said secondnon-silicon layer forming a second layer of said multilayer emitter; asilicon (Si) base layer of a second conductivity type formed in contactwith said second non-silicon layer, wherein an base-emitter transistorjunction is formed at a boundary between said second non-silicon layerand said base layer and wherein said base-emitter transistor junction issubstantially free of interdiffusion; and a Si collector of said firstconductivity type formed adjacent to said base layer.
 15. A verticalheterojunction bipolar transistor as claimed in claim 14 wherein: saidfirst non-silicon layer is configured to have a first region doped toexhibit said first conductivity type, said first region being intrinsicto said heterojunction bipolar transistor; and said first non-siliconlayer is configured to have a second region which is substantiallyinsulative, said second region being extrinsic to said heterojunctionbipolar transistor.
 16. A vertical heterojunction bipolar transistor asclaimed in claim 14 wherein said second non-silicon layer is galliumarsenide (GaAs).
 17. A vertical heterojunction bipolar transistor asclaimed in claim 14 wherein said second non-silicon layer is coherentlystrained between said silicon base layer and said first non-siliconlayer.
 18. A vertical heterojunction bipolar transistor as claimed inclaim 17 wherein said second non-silicon layer is gallium arsenide(GaAs) and has a thickness of less than 200 Å.
 19. A verticalheterojunction bipolar transistor as claimed in claim 14 wherein saidfirst non-silicon layer is gallium phosphide (GaP).
 20. A verticalheterojunction bipolar transistor as claimed in claim 14 wherein saidtransistor additionally comprises a Si substrate, wherein said firstnon-silicon layer is formed over said Si substrate.
 21. A verticalheterojunction bipolar transistor as claimed in claim 20 wherein: saidfirst non-silicon layer is formed substantially of gallium phosphide(GaP); said first non-silicon layer is configured to have a first regiondoped to exhibit said first conductivity type, said first region beingin contact with said second non-silicon layer; and said firstnon-silicon layer is configured to have a second region proximate saidSi substrate, said second region not being doped to exhibit said firstconductivity type.